The development of hybrid bipolar/CMOS technologies is in many cases based on an existing CMOS process. Accordingly, a completely new concept of a hybrid technology is rare. In all cases, an economic compromise between transistor performance parameters and process complexity can be found.
In accordance with the multitude of possible applications, there is already a broad spectrum of BiCMOS processes, which differ significantly in their level of complexity. For instance, up to 25 mask levels may be necessary to implement vertical npn and pnp transistors together with CMOS devices in double-polysilicon technology.
Attempts have been made to limit the process complexity in the hybrid technologies, but to date, these methods have not proven very successful. For instance, if buried low-resistivity collector regions are used, this necessitates incorporating an epitaxial layer into the CMOS process, which is a cost-intensive and yield-reducing process step.
An article entitled "New CMOS Technologies", published in "Solid-State Devices", 1980, pages 114 to 117, discloses a method for making a monolithic integrated circuit with at least one pair of complementary Si-gate field-effect transistors and at least one planar npn bipolar transistor. In a thick oxide layer disposed on the substrate, openings are formed through which, using a mask against ion implantation, ions are locally implanted to choose the threshold voltage of the transistors and the field threshold voltage between the transistors. In addition to the steps used in the conventional Si-gate CMOS process, a further masking and implantation process is carried out to dope the base regions of the bipolar transistor. This implantation takes place through a thin oxide layer which is formed simultaneously with the thin oxide layers in the areas of the field-effect transistors. With respect to the bipolar transistor, the known method has the disadvantage of a compensated emitter. Furthermore, the bipolar transistor takes up considerable more space than the field-effect transistors.
The increased space requirement referred to above is mainly due to the necessary alignment tolerances. Both the alignment of the base region with respect to the collector contact and that of the emitter region with respect to the base are critical in the known method.
U.S. Pat. No. 4,475,279 to Gahle, entitled METHOD OF MAKING A MONOLITHIC INTEGRATED CIRCUIT COMPRISING AT LEAST ONE PAIR OF COMPLIMENTARY FIELD-EFFECT TRANSISTOR AND AT LEAST ONE BIPOLAR TRANSISTOR and assigned to IIT Industries, Inc. discloses a method for producing a monolithic integrated circuit having field effect transistors (FETs) and bipolar transistors. A space saving is achieved by dividing the opening of the bipolar transistor by means of a stripelike thin oxide layer. The method is advantageous in that it permits self-aligning and/or critical processes. A disadvantage of the method is the unpassivated gate oxide, which is easily damaged and contaminated. Moreover, additional photomasking steps are necessary to open the collector and emitter windows.
It is, therefore, an object of the invention to provide a modified method which reduces the number of manufacturing steps necessary to produce a Bi-CMOS transistor device. It is further an object of the present invention to provide a simplified manufacturing process in which the likelihood of damage and contamination to the integrated circuit devices is reduced.